Presently, multilevel inverters are popular in a medium power application. As the voltage level increases, the number of identical Flying Capacitor (FC) increases exponentially. This causes reliability issues for higher level outputs in the multilevel inverter. The size of the FCs depends upon line frequency as well. Thus, it is necessary to develop a new topology with less number of identical FCs, optimum number of switches and smaller size of FCs such that, there is enough redundancy states available to charge and discharge the FCs for each voltage level.
Further, with increase in voltage levels, the number of semiconductor devices increase exponentially. This causes reliability issues for higher level outputs. With the increase in number of semiconductor devices, the total conduction losses are also increased. There is a requirement for developing a topology with optimum number of semiconductor devices and lower conduction losses in comparison with existing topologies.
The above information is presented as background information only to help the reader to understand the present invention. Applicants have made no determination and make no assertion as to whether any of the above might be applicable as Prior Art with regard to the present application.